FIGS. 4(a)-4(c) are sectional views showing main steps for forming a GaAs (gallium arsenide) layer on a Si substrate, which is disclosed in, for example Japanese Journal of Applied Physics Vol. 25 Sep., 1986, L789-L791 "Effects of the Substrate Offset Angle on the Growth of GaAs on Si substrate".
In those figures, reference numeral 1 designates a Si substrate having surface orientation which is off angle by several degrees from a (100) surface toward the &lt;011&gt; direction, reference numeral 2 designates a GaAs layer grown at low temperature (400.degree. C.), reference numeral 4 designates a GaAs layer grown at high temperature (700.degree. C.).
Next, a method for manufacturing those will be described in detail.
First, a surface of the Si substrate 1 is cleaned in a hydrogen (H.sub.2) atmosphere at 900.degree. C. or more (FIG. 4(a)). Then, the Si substrate 1 is cooled and a GaAs layer is grown thereon at approximately 400.degree. C. by the MOCVD method to a thickness of 100.ANG. (FIG. 4(b)). Thereafter, the Si substrate 1 is heated up at 700.degree. C. and then the GaAs layer 4 is grown to a thickness of 2 microns by the MOCVD method on the GaAs layer 2 which has been grown at low temperature (FIG. 4(c)).
However, in a case where a crystal is grown on different kinds of substrates, typical of a case where the GaAs layer is formed on the Si substrate, three-dimensional growth of GaAs is likely to occur because stress is generated by the difference in lattice constant of Si and GaAs or surface orientation growth rate dependency. If the GaAs layer is grown at low temperature (.about.400.degree. C.), crystal quality is low but it is possible to prevent generation of three-dimensional crystal which is likely to occur because of the surface orientation dependency of the crystal growth or rate or stress generated by a difference in the lattice constants. More specifically, at low temperature, when a crystal is grown under the condition of chemical non-equilibrium, surface orientation dependency or three- dimensional crystal growth is not likely to occur, so that the plane two-dimensional GaAs crystal 2 can be easily obtained. Therefore, it is possible to form a GaAs layer 4 of high quality having good coverage by forming the thin GaAs layer 2 at low temperature first to flatten the surface of the Si substrate and then forming the GaAs layer at high temperature.
As described above, in the conventional method for growing the GaAs layer on the Si substrate, means for forming the plane GaAs layer 4 on the Si substrate is provided. However, abnormal growth of GaAs is not effectively prevented as shown in FIG. 5, taken from a photograph), in which there is abnormal growth of GaAs on the (100) surface of the GaAs crystal. In FIG. 5, reference numeral 4a designates a (100) surface of the GaAs layer 4 and reference numeral 13 designates a pit around which there is abnormal growth of GaAs.
Thus, when there is dust or other defects (pit) on the Si substrate 1, GaAs is abnormally grown. FIG. 6(a) is a plan view showing abnormal growth of GaAs around a defect of the Si substrate surface just after GaAs is sequentially grown at low and high temperature on the Si substrate 1 and FIG. 6(b) is a sectional view taken along a line VIb-VIb of FIGS. 6(a)-6(c). In FIG. 6, the same references as in FIG. 4 designate the same parts. Reference numeral 4a designates a (100) surface of the GaAs layer 4 grown at high temperature, reference numeral 4b designates a (111) surface of the GaAs layer 4 grown at high temperature, reference numeral 13 designates a pit and reference numeral 1a designates an exposed Si (100) surface. As shown in FIGS. 6(a)-6(c), the GaAs layer 4a of is grown on the Si substrate which is off angle by of several degrees from the (100) surface towards the &lt;011&gt; direction. However, if there is a defect on the Si surface, GaAs is not likely to be grown at that defect and the GaAs (111) surface 4b is actively grown around that defect, with the result that a trench 13 surrounded by the abnormally grown GaAs (111) surface is formed.
In addition, when the GaAs layer is formed on the Si substrate, since my thermal expansion coefficient of GaAs is more than twice that of Si (Si ; 2.4.times.10.sup.-6 [K.sup.31 1 ], GaAs ; 5.7.times.10.sup.-6 [K.sup.-1 ]), thermal stress of approximately 1.times.10.sup.9.about. 2.times.10.sup.9 dyn cm.sup.-2 remains in the GaAs layer, causing the substrate to be curved. In addition, the intensity of this stress is very close to the rupture strength of the GaAs layer 4 and when this thermal stress converges around the abnormal growth of GaAs, a crack is likely to be generated in the GaAs layer. As a result, performance or yield of the semiconductor device is considerably lowered. FIG. 6(c) shows a curved substrate, in which the crack 14 is generated in the pit 13 because of the difference between the thermal expansion coefficients of Si and GaAs. At this time, the temperature has dropped from that in FIG. 6(b). Therefore, it is necessary to limit the thickness of the GaAs layer 4 to 3.0 microns or less to prevent the remaining thermal stress in the GaAs layer from converging at the pit 13 on the GaAs substrate surface and a crack from being generated.
FIGS. 7(a) and 7(b) show the abnormal growth of GaAs around the surface defect of the Si substrate and the crack generated at that abnormally grown part taken from photographs in which the same reference numerals as in FIG. 6(a) designate the same parts. As shown in FIG. 7(a), it is found that crack 15 is generated through the pit 13 of the GaAs layer.